SK Hynix CPO roadmap targets 100 Tb/s as AI scales

SK Hynix published a co-packaged optics (CPO) roadmap in Nature Electronics on Aug. 20 that extends optical interconnects to memory interfaces, targeting more than 100 Tb/s of bandwidth per node as AI competition shifts from single chips to entire systems.

"Even if computing chips become more powerful, overall system performance cannot improve unless data movement between chips keeps pace," Kyusang Lee, a professor of electrical and computer engineering at the University of Virginia and a corresponding author, said.

The paper, written with researchers from MIT, the University of Illinois Urbana-Champaign, Nanyang Technological University and Yonsei University, argues compute throughput has tripled every two years while interconnect bandwidth advanced only 1.4-fold, creating what it calls a "bandwidth wall." CPO integrates optical transceivers into the processor package, compressing the distance high-speed electrical signals must travel. The authors set targets of energy below 1 picojoule per bit and chip-to-chip latency under 10 nanoseconds.

SK Hynix shares surged more than 11 percent on the announcement, and CPO concept stocks in China rallied, with T&S Communications up over 12 percent. The roadmap marks the memory maker's move beyond HBM into system-level architecture, joining TSMC, Intel and Broadcom, which are all investing in CPO.

The bandwidth wall copper can't cross

Hyperscale AI models now run across networks of racks and pods rather than single servers, so system performance depends on how efficiently data moves between them. Copper-based electrical interconnects, which carry data beyond the chip package, suffer rising signal loss and power consumption as transmission distances grow, requiring increasingly complex compensation circuitry that adds latency.

CPO answers this by placing optical engines inside the same package as the processor. High-speed electrical signals travel only a short distance before handing off to optical links, which carry data across chips, racks and pods with lower loss and stronger immunity to electromagnetic interference. The paper maps the technology's evolution from 2D and 2.5D interposer configurations to 3D heterogeneous stacking, itemizing the challenges for commercial deployment.

From HBM supplier to system architect

The paper's most ambitious proposal is an optics-centric architecture using a photonic interposer to connect a processor resource pool directly with a memory resource pool. Multiple AI accelerators could share one large-capacity memory pool rather than each carrying dedicated HBM stacks, breaking the physical limits of packaging that constrain how much memory can sit beside a GPU.

"Extending optical interconnects to the memory interface would overcome the physical constraints surrounding compute chips, removing limitations on both memory capacity and the number of electrical connections," Lee said. Seunghoon Hong, head of SK Hynix's AI Infrastructure team and the other corresponding author, said the approach lets AI systems scale more flexibly by improving data movement efficiency.

HBM solved the memory bottleneck inside AI accelerator packages and has been SK Hynix's core strength for years. The CPO roadmap extends that franchise into system-level design. "Memory companies are evolving from the role of providing individual components to becoming partners that help strengthen the competitiveness of customers' entire systems," Hong said.

The shift carries competitive weight. TSMC, Intel and Broadcom are all investing in CPO, and Nvidia's GPU roadmaps depend on the interconnect fabric that surrounds them. SK Hynix, which supplies HBM to Nvidia, is moving to shape that fabric rather than just fill it. Lee acknowledged commercialization still faces hurdles, from integrating low-power photonic devices to developing coherence protocols and improving system reliability.

SK Hynix shares, which rose more than 11 percent on the paper's publication, trade as one of the highest-valued memory makers on expectations that AI demand keeps HBM supply tight. The CPO roadmap extends that thesis: if optical interconnects become a standard part of AI infrastructure, SK Hynix's role grows from component vendor to architect of the data path, a position that could command higher margins than commodity memory. The technology remains years from large-scale deployment, but the direction of travel is clear.

This article is for informational purposes only and does not constitute investment advice.