Samsung to use 2nm GAA in HBM5, targeting 50% speed boost

Samsung Electronics will embed its 2nm Gate-All-Around process into the base die of its eighth-generation HBM5 memory, targeting a more than 50% speed improvement over HBM4E and challenging SK Hynix's lead in the AI memory market.

"The HBM5 base die will employ the 2nm process using a GAA structure, enabling a higher-density through-silicon via implementation," Koo Ja-heum, executive vice president and head of technology development at Samsung's foundry business, said in a July 27 interview published on the company's newsroom.

Samsung previously used its 4nm fourth-generation process for the HBM4 and HBM4E base dies, achieving data processing speeds of 14 Gbps. The jump to 2nm GAA — a transistor architecture where the gate surrounds all four sides of the current channel, improving performance per watt — represents two full node jumps. Samsung began mass production of its first-generation 2nm process in the second half of 2025 and plans to start second-generation 2nm production for new mobile products in the second half of 2026.

The move comes as Samsung seeks to reclaim market share in the HBM segment, where SK Hynix has held a dominant position supplying Nvidia's AI accelerators. Samsung's integrated device manufacturer model — combining memory, foundry, and packaging under one roof — allowed it to complete the HBM4 base die sample in roughly three months, a timeline the company says is difficult for pure-play foundries like TSMC to match.

A $200 Billion Bet on Vertical Integration

The HBM5 roadmap follows a string of major partnership wins. On July 24, Samsung announced a five-year strategic agreement with Broadcom valued at more than $200 billion through 2030, covering 2nm and sub-2nm foundry services, next-generation HBM4 memory, and advanced 2.3D and 2.5D packaging. The deal directly challenges TSMC's foundry dominance by offering Broadcom a full-stack solution that reduces supply chain friction.

Samsung has also secured orders from Tesla for automotive-grade 2nm chips and from multiple AI and high-performance computing customers, according to Koo. The company is supplying HBM4 for AMD's Helios infrastructure platform and the MI455X accelerator, which uses TSMC's 2nm and 3nm chiplet technology. A single Helios rack integrates 31 terabytes of HBM4 memory, with initial shipments starting at the end of the third quarter.

What the 2nm Transition Means for the AI Memory Market

The shift to 2nm GAA for HBM base dies addresses a growing bottleneck in AI accelerator design. As GPU compute density increases, the interface between memory stacks and processors must keep pace without consuming disproportionate power. Samsung's GAA architecture allows more precise current control than the FinFET structure used in its 4nm base dies, enabling higher-density through-silicon vias that pack more bandwidth into the same footprint.

For investors, the question is whether Samsung can convert its technology roadmap into market share gains. SK Hynix has dominated the HBM3 and HBM4 cycles, securing long-term supply agreements with Nvidia. Samsung's HBM5 timeline — with 2nm GAA base dies and a more than 50% speed improvement — represents its clearest attempt to leapfrog the competition in the next memory generation. Samsung shares trade at a discount to SK Hynix on a price-to-earnings basis, reflecting the market's skepticism about its foundry turnaround. The Broadcom deal and HBM5 roadmap could narrow that gap if Samsung delivers on its production targets.

This article is for informational purposes only and does not constitute investment advice.