Huawei Targets 1.4nm Chips by 2031 With New Sanctions-Busting Design

(P1) Chinese technology giant Huawei Technologies Co. unveiled a new chip design framework that it claims will match the performance of 1.4-nanometer chips by 2031, a move aimed at sidestepping US sanctions that block its access to the world’s most advanced manufacturing equipment.

(P2) "Over the past six years, I have often been asked... how did you survive and come back on top?" He Tingbo, chairwoman of Huawei’s HiSilicon semiconductor division, said in a presentation at the International Symposium on Circuits and Systems in Shanghai.

(P3) The new method replaces the industry's long-standing Moore’s Law with a "Tau Scaling Law," which prioritizes signal speed over shrinking transistor sizes. This is executed through a proprietary "LogicFolding" architecture that physically stacks logic circuits, a technique the company says it has validated with 381 experimental chips. The first commercial processor using the design will be a new Kirin chip debuting this autumn.

(P4) The announcement sent shares of Chinese chipmakers soaring, with Semiconductor Manufacturing International Corp. (SMIC) and Hua Hong Semiconductor Ltd. jumping nearly 15% in Hong Kong trading. The development signals a potential breakthrough in China's push for technological self-sufficiency and intensifies the high-stakes rivalry with the US for dominance in artificial intelligence and advanced computing.

A New Path to Advanced Chips

Huawei’s announcement suggests it may have found a viable workaround to its most significant barrier: the lack of access to extreme ultraviolet (EUV) lithography machines. These sophisticated tools, primarily made by Dutch firm ASML Holding NV, are considered essential for mass-producing chips at the 5-nanometer node and below. US export controls have effectively cut off all Chinese firms, including Huawei and foundry partner SMIC, from acquiring EUV systems.

Instead of pursuing the geometric scaling of Moore's Law, which focuses on cramming more transistors into a smaller space, Huawei's "temporal scaling" framework optimizes how rapidly data moves across the chip. By folding and stacking circuits in a dual-layer framework, the company shortens internal wiring to reduce signal delay. While Huawei claims this results in major efficiency gains, it did not disclose the specific test conditions for its performance metrics.

Competitive Timeline and Investor Reaction

The 2031 target for a 1.4-nanometer equivalent chip places Huawei about three years behind the current public roadmap of industry leader Taiwan Semiconductor Manufacturing Co. (TSMC), which projects it will reach the 1.4nm node by 2028. However, if successful, it would represent a monumental achievement for China's sanctioned tech champion, significantly mitigating the impact of the US restrictions.

"It’s an alternative path forward, and a breakthrough Huawei managed to find while facing supply chain challenges," Omdia analyst Lian Jye Su told the Wall Street Journal.

Investors reacted with immediate enthusiasm, seeing the technology as a catalyst for the entire domestic semiconductor ecosystem. The surge in SMIC's stock price reflects expectations that it will be the primary manufacturer for Huawei's new designs. The development poses a long-term competitive challenge to global leaders like TSMC, Samsung Electronics Co., and Nvidia Corp., whose advanced GPUs currently power the AI revolution. Huawei plans to adapt the LogicFolding architecture for its Ascend AI processors, with a goal of deploying them in data centers by 2030.

This article is for informational purposes only and does not constitute investment advice.