Key Takeaways:
IBM Research has produced the world's first sub-1 nanometer chip architecture, packing nearly 100 billion transistors onto a fingernail-sized die and extending the semiconductor roadmap into the angstrom era.
IBM's new nanostack architecture, built at the 0.7-nanometer node, delivers up to 50% higher performance or 70% greater energy efficiency than its 2nm predecessor — a leap that could reshape the economics of AI data centers.
"It's not just an incremental step, it's a meaningful leap forward, pointing to a future where computing becomes significantly more powerful without a corresponding increase in energy," Jay Gambetta, director of IBM Research and an IBM Fellow, said.
The nanostack design stacks transistors vertically rather than laying them side by side, enabling nearly twice the transistor density of IBM's 2nm node chip introduced in 2021. IBM also demonstrated a 40% improvement in SRAM scaling, a critical metric for AI workloads that rely on high-bandwidth, low-latency memory. The architecture allows top and bottom transistors to be engineered separately with different materials, unlocking performance and power optimizations impossible in conventional planar designs.
IBM no longer manufactures chips commercially — it exited fabrication in 2015 by transferring its plants to GlobalFoundries — but its research pipeline has historically set the direction for the entire industry. Nanosheet technology, which IBM pioneered, now underpins all leading-edge 3nm and 2nm chips from TSMC and Samsung Foundry. If nanostack follows the same trajectory, it could influence the next decade of chip design for Nvidia, AMD, and Intel.
How Nanostack Works
The basic unit of IBM's nanostack architecture consists of two transistors stacked and bonded together, each containing three nanosheets individually 5 nanometers thick — equivalent to about 15 rows of silicon atoms. By staggering transistors in the vertical dimension, IBM effectively adds a third axis to chip scaling that the industry has largely exhausted in two dimensions since the transistor was invented in 1959.
"This will be for the first time in our industry that we are able to stack and stagger transistors in a vertical direction," Huiming Bu, vice president of silicon technology research and development at IBM, said.
The approach addresses a fundamental problem: traditional transistor miniaturization has approached atomic limits, and SRAM scaling — the ability to shrink the memory cells closest to the processor — had slowed to just a few percent between the 3nm and 2nm generations. IBM's 40% SRAM improvement through staggered-channel bit cells represents a step-change in an area where progress had nearly stalled.
The AI Data Center Connection
The timing of the breakthrough aligns with an inflection point in AI infrastructure spending. Nvidia's Blackwell GPU, built on TSMC's 4nm node, and the coming Rubin platform on 3nm, both push against power and thermal constraints in data centers. Hyperscalers including Microsoft, Amazon, and Alphabet are spending tens of billions annually on GPU clusters, where energy costs have become a binding constraint on expansion.
"Everyone demands more performance, but no one wants to pay for the bill for the power," Bu said.
IBM's SRAM improvements are particularly relevant because many AI chips dedicate large portions of die area to on-chip memory to reduce data movement — one of the largest sources of energy consumption in AI inference. More efficient SRAM designs could increase cache capacity and reduce the need to shuttle data between processors and external memory, directly lowering the total cost of ownership for AI workloads.
Path to Commercialization
IBM cautioned that the technology remains in the research phase, with earliest adoption at the sub-1nm node expected within five years. The company is working with partners including Japan's Rapidus on 2nm manufacturing and is preparing to use ASML's High NA EUV lithography tools at its Albany, New York facility — equipment that will be essential for printing the ultra-precise circuit patterns that nanostack requires.
Gambetta declined to name specific commercialization partners but said the architecture is generic enough to apply across CPUs, GPUs, and mobile processors. "Within a decade, this will become another mainstream that we have invented and helped industry to transform," Bu said.
For investors, the question is whether nanostack follows the nanosheet playbook — where IBM's research became the industry standard adopted by TSMC and Samsung — or remains a lab curiosity. IBM shares trade at roughly 22x forward earnings, with the stock's valuation driven more by its software and consulting businesses than its semiconductor intellectual property. A successful licensing pipeline for nanostack could add a new revenue stream, though the company has not disclosed any licensing agreements.
This article is for informational purposes only and does not constitute investment advice.
