TSMC pulls 3nm ramp forward 2-3 months to 180,000 wafers

TSMC is pulling its 3nm capacity ramp two to three months forward to 180,000 monthly wafer starts by early Q4, as Nvidia, AMD and Broadcom race to lock in allocation.

TSMC is pulling its 3nm capacity ramp two to three months forward, targeting 180,000 monthly wafer starts by early Q4, as Nvidia, AMD and Broadcom compete for scarce advanced-node output. The world's largest foundry, holding about 70 percent of the market, is converting older 5nm lines to meet demand that has pushed its most advanced process to reported gross margins above 60 percent.

"The 180,000 figure is a reported ramp estimate, not confirmed TSMC guidance, but even the directional signal is significant — a greater-than-40 percent year-on-year increase in output at the world's most advanced logic node," according to TrendForce, the Taipei-based market research firm tracking the ramp.

Nvidia alone is absorbing roughly 35,000 additional wafers per month, the clearest single indicator of how fast accelerator demand is running. AMD, Broadcom and Apple are each racing to secure allocation alongside it. TSMC is responding by converting older-node lines and advancing a new Southern Taiwan 3nm fab targeting a first-half 2027 opening. The ramp lifts N3 output from roughly 120,000-130,000 wafers a month at the end of 2025.

The acceleration is a pricing-power story dressed in capacity statistics. When a non-substitutable input is in short supply, the incumbent captures the surplus — and TSMC, with a market value near $2.16 trillion, has no credible second source at this node. Intel Foundry trails on yield and Samsung Foundry on competitive parity, leaving every accelerator designer with a single queue to join.

The two-chokepoint structure of the AI supply chain makes the ramp's significance legible. At the base sits memory — DRAM and HBM — a contestable input with a commodity floor that China's CXMT is actively flooding. Leading-edge logic has no such floor. There is exactly one company that can manufacture an Nvidia H100-successor or an AMD MI-series accelerator at 3nm, at volume, at yield: TSMC.

More 3nm wafers only partially ease the broader AI chip crunch. Advanced packaging — specifically CoWoS (Chip on Wafer on Substrate) — and high-bandwidth memory remain the tighter bottlenecks in the full accelerator supply chain. The supply chain's tightest point shifts; it does not disappear.

2nm ramps behind 3nm

Behind the 3nm push, TSMC is doubling its 2nm output. N2 wafer production, roughly 50,000-60,000 in the first half of 2026, is expected to reach 100,000 monthly by year-end. The node currently accounts for about 3 percent of revenue, versus roughly 30 percent for N3 and 33 percent for N5, but adoption is broadening: Apple's A20 and A20 Pro SoCs for the iPhone 18 series, AMD's Instinct MI450 and Nvidia's Rubin Ultra all run on 2nm.

What it means for investors

TSMC shares rose more than 2 percent on the news. The stock trades at about 30 times trailing earnings, above its five-year median of roughly 23 times, and GuruFocus pegs its GF Value at $302.92 against a price near $417 — a 37.7 percent overvaluation that leaves little margin of safety. The capacity expansion is bullish for the broader semiconductor supply chain, potentially easing constraints for downstream AI hardware makers, while pressuring Samsung Foundry, which trails on 3nm parity and lost Tesla's next-gen A15 AI chip tape-out to TSMC by roughly a quarter.

Every wafer TSMC adds at N3 deepens the world's dependence on a single fab network in Taiwan. The Southern Taiwan facility and overseas expansions in Arizona, Japan and Germany are genuine diversification efforts, but they are measured in years and will not produce N3-equivalent yield at comparable scale on any near-term horizon.

This article is for informational purposes only and does not constitute investment advice.